Topic: Proper LF tag emulation support
I'm wanting to properly emulate a LF tag on the Proxmark3 (Hitag2, specifically) with full bidirectional communication between tag and reader and am suspecting that the current FPGA code does not really support this. Also, I haven't seen any documentation with regards to the currently supported FPGA major modes, so let me first state what I think I understood from reading the source and then you can correct me:
The only modes accessing the LF path are FPGA_MAJOR_MODE_LF_READER (corresponding to lo_read.v), FPGA_MAJOR_MODE_LF_SIMULATOR (lo_simulate.v) and FPGA_MAJOR_MODE_LF_PASSTHRU (lo_passthru.v)
lo_read.v and lo_passthru.v both actively drive the antenna, so are useless for simple tag emulation
lo_simulate.v connects the AT91SAM7 SSC output to PWR_OE{1,2,4}, sets PWR_OE3 to 0 and sets PWR_LO to low. As far as I can tell the output enable on the coil drivers is inverting, so setting PWR_OE3=0 and PWR_LO=0 continously drives the antenna at GND level. When the AT91SAM7 has SSC_DOUT set to high the remaining output drivers are in tri-state, otherwise they too will drive the antenna to GND level. For some reason though, SimulateTagLowFrequency() calls these two states OPEN_COIL and SHORT_COIL. The AT91SAM7 SSC clock input is connected to CROSS_LO which (through a buffer) directly comes from the antenna (if the relay is switched to the peak detect path).
So, the lo_simulate.v code can switch the LF antenna between slightly connected to GND and strongly connected to GND, and gives the unfiltered carrier as a clock signal to the AT91SAM7.
Now, in theory the carrier signal would be good enough to receive. I even came up with an elaborate plan to use the AT91SAM7's timer/counter unit as a kind of envelope detector. Alas, I just looked at the signal on an oscilloscope, and it's completely useless. The clock signal is there, regardless of whether the carrier is currently full or modulated, it just gets worse during the modulation phase. Even when the carrier is completely off for a prolonged period of time there are glitches on that line. That's due to the fact that the proxmark only has an opamp between the antenna signal and CROSS_LO, a Schmitt-Trigger (as seen on the OpenPICC) would be better.
Now, looking around, I fear that a change to the FPGA code is necessary, so any advice would be great. I haven't done any FPGA or Verilog yet, ever.
What I guess would be great would be an envelope detector on the FPGA, working off the LORAW signal. However, looking at that signal on the scope, it too seems to be useless because it's either at maximum or at minimum all the time. Instead, looking at the LOPKD signal, this can probably be used. I admit that I have no idea how the peak detection circuitry works, but I think it would be possible to use that signal. Now, in the FPGA I need either (or both) a configurable threshold on the A/D values, or a mode to submit the A/D values through the SSC onto the AT91SAM7, much like the existing lo_read code, but without driving the antenna. The latter would allow the (possibly dynamic) threshold to be computed in the AT91SAM7.
